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Micrel, Inc.
Pin Description: Signal Descriptions by Group (Continued)
KSZ9692PB, KSZ9692PB-S
Pin Number
Pin Name
Pin Type
Pin Description
Ethernet Port 0
M16
P0_RXC
Ipd/O
MAC mode MII: input RX clock / PHY mode MII: output RX clock
RGMII mode: input RX clock
P18, N17,
P0_RXD[3:0]
I
RX data[3:0]
P17, N16
N18
P0_RXDV
I
MII mode: RX data valid
RGMII mode: as RX_CTL. RXDV on rising edge of RXC, logic derivative of
RXDV and RXER on falling edge of RXC
P19
P0_RXER
I
MII mode: RX error
RGMII mode: input SEL
M17
P0_CRS
I
MAC mode MII: input carrier sense
RGMII mode: not used
P20
P0_COL
I
MAC mode MII: input collision
RGMII mode: not used
M18
P0_TXC
Ipd/O
MAC mode MII: input TX clock / PHY mode MII: output TX clock
RGMII mode: output TX clock
L17, M19,
P0_TXD[3:0]
O
TX data[3:0]
N20, N19
L16
P0_TXEN
O
MII: TX enable
RGMII: as TX_CTL input. TXEN on rising edge of TXC, logic derivative of
TXEN and TXER on falling edge of TXC.
Ethernet Port 1
K19
P1_RXC
Ipd/O
MAC mode MII: input RX clock / PHY mode MII: output RX clock
RGMII mode: input RX clock
L20, L19,
P1_RXD[3:0]
I
RX data[3:0]
L18, M20
K16
P1_RXDV
I
MII mode: RX data valid
RGMII mode: as RX_CTL. RXDV on rising edge of RXC, logic derivative of
RXDV and RXER on falling edge of RXC
K17
P1_RXER
I
MII mode: RX error
RGMII mode: input SEL
K18
P1_CRS
I
MAC mode MII: input carrier sense
RGMII mode: not used
K20
P1_COL
I
MAC mode MII: input collision
RGMII mode: not used
J17
P1_TXC
Ipd/O
MAC mode MII: input TX clock / PHY mode MII: output TX clock
RGMII mode: output TX clock
H20, J19,
P1_TXD[3:0]
O
TX data[3:0] output.
J18, J20
J16
P1_TXEN
O
MII: TX enable
RGMII: as TX_CTL input. TXEN on rising edge of TXC, logic derivative of
TXEN and TXER on falling edge of TXC.
May 2011
14
M9999-051111-4.0
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